View AD7699_827099.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16 - bit, 8 - channel, 500 ksps pulsar adc AD7699 rev. 0 information furnished by analog devices is belie ved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no li cense is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 78 1.329.4700 www.analog.com fax: 781.461.3113 ? 2008 analog devices, inc. all rights reserved. features 16- bit resolution with no missing codes 8- channel multiplexer with choice of inputs unipolar s ingle -e nded d ifferential (gnd sense) p seudo b ipolar throughput: 500 ksps inl: 0. 5 lsb typical , 1.5 lsb m ax imum ( 23 ppm or fsr) dynamic range: 93.3 db sinad: 91.5 db @ 20 khz thd: ?97 db @ 20 khz a nalog input range: 0 v to v ref with v ref up to vdd multiple reference types internal 4.096 v external buffered (up to 4.096 v) external (up to vdd) internal temperature sensor channel sequencer, selectable 1 - pole filter, busy indicator no pipeline delay , sar architecture single - supply 5 v operation with 1.8 v to 5 v logic interface serial interface compatible with spi , microwire , qspi, and dsp power dissipation 26 mw @ 5 00 ksps 5.2 w @ 100 sps standby current: 50 na 20- lead 4 mm 4 mm lfcsp package applications battery - powered equipment medical instruments : ecg /ekg mobile communications : gps personal digital assistants power line monitoring data acquisition seismic data acquisition systems i nstrumentation process c ontrol functional b lock diagram AD7699 ref gnd vdd vio din sck sdo cnv 1.8v to vdd 5v sequencer spi serial interface mux 16-bit sar adc band gap ref temp sensor refin in0 in1 in4 in5 in6 in7 in3 in2 com 0.5v to vdd 10f one-pole lpf 0.5v to 4.096v 0.1f 07354-001 figure 1. table 1 . multichannel 14 - /16 - bit pulsar ? adc type channels 250 ksps 500 ksps adc driver 14- bit 8 ad7949 ada4841 -x 16- bit 4 ad7682 ada4841 -x 16- bit 8 ad7689 a d7699 ada4841 -x general description the ad 7699 is an 8- channel , 16 - bit, charge redistribution succes si ve approximation register (sar) analog - to -digital converter (adc) that operate s from a single power supply, vdd. the AD7699 contain s all components for use in a multi channel, low power dat a acquisition system , including a true 16 - bit sar adc with no missing codes; a n 8- channel low crosstalk multip - lexer useful for configurin g the inputs as single - ended (with or without ground sense), differential , or bipolar; an internal 4.096 v low drift reference and buffer ; a temperature sensor ; a selectable one - pole filter; and a sequencer that is useful when channels are continuously scanned in order. the AD7699 uses a simp le serial port interface ( spi ) for writing to the configuration register and receiving conver sion results . the spi interface uses a separate supply, vio , which is set to the host logic level. p ower dissipation scales with throughput. the AD7699 is housed in a tiny 2 0- lead lfcsp with operation specified from ?40c to +85c.
AD7699 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications ....................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 12 ? theory of operation ...................................................................... 13 ? overview ...................................................................................... 13 ? converter operation .................................................................. 13 ? transfer functions...................................................................... 14 ? typical connection diagrams .................................................. 15 ? analog inputs .............................................................................. 16 ? driver amplifier choice ............................................................ 18 ? voltage reference output/input .............................................. 18 ? power supply ............................................................................... 19 ? supplying the adc from the reference .................................. 19 ? digital interface .............................................................................. 20 ? reading/writing during conversion, fast hosts .................. 20 ? reading/writing during acquisition, any speed hosts ...... 20 ? reading/writing spanning conversion, any speed host .... 20 ? configuration register, cfg .................................................... 20 ? general timing without a busy indicator ............................. 22 ? read/write spanning conversion without a busy indicator ...................................................................................... 23 ? general timing with a busy indicator ................................... 24 ? read/write spanning conversion with a busy indicator ..... 25 ? application hints ........................................................................... 26 ? layout .......................................................................................... 26 ? evaluating AD7699 performance ............................................. 26 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 10/08revision 0: initial version
AD7699 rev. 0 | page 3 of 28 specifications vdd = 4.5 v to 5.5 v, v ref = 4.096 to vdd, vio = 1.8 v to vdd, all specifications t min to t max , unless otherwise noted. table 2. parameter conditions/comments min typ max unit res olution 16 bits analog input voltage range unipolar mode 0 +v ref v bipolar mode ?v ref /2 +v ref /2 v absolute input voltage positive input, unipolar and bipolar modes ?0.1 v ref + 0.1 v negative or com input, unipolar mode ?0.1 + 0.1 v nega tive or com input, bipolar mode v ref /2 ? 0.1 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 68 db leakage current at 25c input impedance 1 acquisition phase 1 na throughput conversion rate full bandwidth 2 0 500 ksps ? bandwidth 2 0 125 ksps transient response full - scale step , full bandwidth 400 ns full - scale step, ? bandwidth 1600 ns accuracy no missing codes 16 bits integral linearity error ? 1.5 0.5 + 1.5 lsb 3 differential l inearity error ?1 0.25 + 1.5 lsb transition noise ref = vdd = 5 v 0.5 lsb gain error 4 all modes ?10 1 +10 lsb gain error match ?3 1 +3 lsb gain error temperature drift 0. 3 ppm/c offset error 4 all modes ?10 1 +10 lsb offset error match ?3 1 +3 lsb offset error temperature drift 0. 3 ppm/c power supply sensitivity vdd = 5 v 5% 1.5 lsb ac accuracy dynamic range 93.3 db 5 signal -to - noise f in = 20 khz, vref = 5 v 92 9 2.5 db f in = 20 khz , vref = 4.096 v internal ref 89.5 91.5 db sinad f in = 20 khz, vref = 5 v 90 91.5 db f in = 20 khz, vref = 5 v, ?60 db input 33.5 db f in = 20 khz, vref = 4.096 v internal ref 89 90.5 db total harmonic distortion f in = 20 khz ? 97 db spurious -fr ee dynamic range f in = 20 khz 11 2 db channel - to - channel crosstalk f in = 100 khz on adjacent channel(s) ?125 db sampling dynamics ?3 db input bandwidth full bandwidth 14 mhz ? bandwidth 3.6 mhz aperture delay vdd = 5 v 2.5 ns
AD7699 rev. 0 | page 4 of 28 parameter conditions/comments min typ max unit internal reference ref output voltage @ 25c 4.086 4.096 4.106 v refin output voltage 6 @ 25c 2.3 v ref output current 300 a temperature drift 10 ppm/c line regulation vdd = 5 v 5% 15 ppm/v long - term drift 1000 hours 50 ppm turn - on s ettling time cref = 10 f 5 ms external reference voltage range ref input 0.5 vdd + 0.3 v refin input (buffered) 0.5 vdd ? 0.2 v current drain 500 ksps, ref = 5 v 100 a temperature sensor output voltage 7 @ 25c 283 mv temperature sensitivity 1 mv/c digital inputs logic levels v il ?0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format 8 pipeline delay 9 v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 4.5 5.5 v vio specified performance 1.8 vdd + 0.3 v standby current 10, 11 vdd and vio = 5 v, @ 25c 50 na power dissipation vdd = 5 v, 100 ksps throughput 5.2 w vdd = 5 v, 500 ksps throughput 26 29 mw vdd = 5 v, 500 ksps throughput with internal reference 28 32 mw energy per conversion 52 nj tempera ture range 12 specified performance t min to t max ?40 +85 c 1 see the analog inputs section. 2 the bandwidth is set with the configuration register. 3 lsb means least significant bit. with the 5 v input range, one lsb = 76.3 v. 4 see the terminology section. these specifications include full temperature range variation but not the error contribution fro m the refere nce. 5 all specifications expressed in decibels are referred to a full - scale input fs r and t ested with an input signal at 0.5 db below full scale, unless otherwise specified. 6 this is the output from the internal band gap. 7 the output voltage is internal and present on a dedicated multiplexer input. 8 unipolar mode: serial 16 - bit straight binary. bipolar mode: serial 16 - bit twos complement. 9 conversion results available immediately after completed conversion . 10 with all digital inputs forced to vio or g nd as required. 11 during acquisition phase. 12 contact an analog devices , inc., sales representative for the extended temperature range.
AD7699 rev. 0 | page 5 of 28 timing specification s vdd = 4.5 v to 5.5 v, v ref = 4.096 to vdd, vio = 1.8 v to vdd , all specifications t min to t max , unless otherwise noted. table 3. parameter 1 symbol min typ max unit conversion time: cnv rising edge to data available t conv 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2 s cnv pulse width t cnvh 10 ns data write/read during conversion t data 1. 2 s sck period t sck t dsdo + 2 ns sck low time t sckl 11 ns sck hi gh time t sckh 11 ns sck falling edge to data remains valid t hsdo 4 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 16 ns vio above 3 v 17 ns vio above 2.7 v 18 ns vio above 2.3 v 21 ns vio above 1.8 v 28 ns cnv low to sdo d15 msb valid t en vio above 4.5 v 15 ns vio above 3 v 17 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns vio above 1.8 v 25 ns cnv high or last sck falling edge to sdo high impedance t dis 32 ns cnv low to sck rising e dge t clsck 10 ns din valid setup time from sck falling edge t sdin 5 ns din valid hold time from sck falling edge t hdin 5 ns 1 see figure 2 and figure 3 for load conditions. i ol 500a 500a i oh 1.4v to sdo c l 50 pf 07354-002 figure 2 . load circuit for digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t de lay 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. 07354-003 figure 3 . volt age levels for timing
AD7699 rev. 0 | page 6 of 28 absolute maximum rat ings table 4. parameter rating analog inputs in x, 1 1 com gnd ? 0.3 v to vdd + 0.3 v or vdd 130 ma ref , refin gnd ? 0.3 v to vdd + 0.3 v supply vol tages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v din, cnv, sck to gnd ?0.3 v to vio + 0.3 v sdo to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance ( lfcsp ) 47.6c/w jc t hermal impedance ( lfcsp ) 4.4c/w 1 see the analog inputs section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD7699 rev. 0 | page 7 of 28 pin configuration and function descrip tions pin 1 indic at or 1 vdd 2 ref 3 r efin 4 gnd 5 gnd 13 sck 14 sdo 15 vio 12 din 11 cnv 6 in4 7 in5 8 in6 01 com 9 in7 81 in2 91 in3 02 vdd 71 in1 61 in0 top view (not to scale) AD7699 07354-004 notes 1. the exposed p addle is not connected internal ly. for increased reliabilit y of the solder joints, it is recommended th a t the p ad be soldered t o the gnd plane. figure 4 . pin configuration table 5 . pin function descriptions pin no. mnemonic type 1 description 1, 20 vdd p power supply. nominally 4.5 to 5.5 v and should be decoupled with 10 f and 100 nf capacitors. 2 ref ai/o reference in put/output. see the voltage reference output/input section. when the internal reference is enabled, this pin produces 4.096 v. when the internal reference is disabled and the buffer is enabled, ref produces a buffered version of t he voltage present on the refin pin (vdd C 0. 5 v maximum) useful when using low cost, low power references. for improved drift performance, connect a precision reference to ref (0.5 v to vdd). for any reference method, this pin needs decoupling with an ext ernal 10 f capacitor connected as close to ref as possible. see the reference decoupling section. 3 refin ai/o internal reference output/reference buffer input. see the voltage reference output/input s ection. when using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 f capacitor. when using the internal reference buffer, apply a source between 0.5 v and 4.096 v that is buffered to the ref pin as previously described. 4, 5 gnd p power supply ground. 6 to 9 in4 to in7 ai analog input channel 4, analog input channel 5, analog input channel 6, and analog input channel 7. 10 com ai common channel input. all input channels , in[7:0], can be refer enced to a common - mode point of 0 v or v ref /2 v. 11 cnv di conversion input. on the rising edge, cnv initiates the conversion. during conversion, if cnv is held high, the busy indictor is enabled. 12 din di data input. this input is used for writing to the 14 - bit configuration register. the configuration register can be written to during and after conversion. 13 sck di serial data clock input. this input is used to clock out the data on s do and clock in data on din in an msb first fashion. 14 sdo do serial data output. the conversion result is output on this pin and synchronized to sck. in unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. 15 vio p input/output interface digital power. no minally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 16 to 19 in0 to in3 ai analog input channel 0, analog input channel 1, analog input channel 2, and analog input channel 3. 21 (epad) exposed paddle (epad ) the exposed paddle i s not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the gnd plane. 1 ai = a nalog i nput, ai/o = analog input/output, di = d igital i nput, do = d igital o utput, and p = p ower .
AD7699 rev. 0 | page 8 of 28 typical performance characteristics vdd = 5v, vref = 5v , vio = vdd, unless otherwise noted 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 16,384 32,768 49,152 65,536 codes (lsbs) 07354-006 figure 5. integral nonlinearity vs. code 250,000 200,000 150,000 100,000 50,000 0 0 0 3 13,341 26,926 10 0 0 counts 7ff9 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 code in hex 07354-005 = 0.51 lsb v ref = 5v 220,840 figure 6. histogram of a dc input at code center 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 25 50 75 100 125 150 175 200 225 250 frequency (khz) amplitude (db of full scale) v ref = 5v f s = 500ksps f in = 19.94khz snr = 92.3db sinad = 91.5db thd = ?98db sfdr = 100db second harmonic = ?111db third harmonic = ?101db 07354-007 figure 7. 20 khz fft, vref = 5 v 1.5 1.0 0.5 0 ?0.5 ?1.0 0 16,384 32,768 49,152 65,536 codes (lsbs) 07354-009 figure 8. differential nonlinearity vs. code 250,000 200,000 150,000 100,000 50,000 0 0 counts 0 119 31,411 157 0 0 = 0.78 lsb v ref = 4.096v 191,013 38,420 7ff9 7ffa 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 code in hex 07354-008 figure 9. histogram of a dc input at code center 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 25 50 75 100 125 150 175 200 225 250 frequency (khz) amplitude (db of full scale) v ref = 4.096v f s = 500ksps f in = 19.94khz snr = 91.1db sinad = 90.4db thd = ?98db sfdr = 100db second harmonic = ?104db third harmonic = ?101db 07354-010 figure 10 . 20 khz fft, vref = 4.096 v
AD7699 rev. 0 | page 9 of 28 100 95 90 85 80 75 70 65 60 0 50 100 150 200 250 300 350 400 450 500 f re quency (khz) snr (db) v ref = 5v ?0.5db ?10db 07354-011 figure 11 . snr vs. frequency ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 0 50 100 150 200 250 300 350 400 450 500 frequency (khz) thd (db) 07354-012 v ref = 5v ?10db ?0.5db figure 12 . thd vs . frequency 96 94 92 90 88 86 ?55 ?35 ?15 5 25 45 65 85 105 125 temper ature (c) snr, sinad (db) f in = 20khz snr, v ref = 5v sinad, v ref = 5v snr, v ref = 4.096v sinad, v ref = 4.096v 07354-013 figure 13 . snr, sinad vs. temperature 100 95 90 85 80 75 70 65 60 0 50 100 150 200 250 300 350 400 450 500 f re quency (khz) sinad (db) v ref = 5v ?10db ?0.5db 07354-014 figure 14 . sinad vs. frequency 16 15 14 13 12 11 10 0 50 100 150 200 250 300 350 400 450 500 frequency (khz) enob (bits) v ref = 5v 07354-015 ?10db ?0.5db figure 15 . enob vs. frequency ?80 ?85 ?90 ?95 ?100 115 110 105 100 95 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) thd (db) sfdr (db) 07354-017 sfdr, v ref = 5v sfdr, v ref = 4.096v thd, v ref = 5v thd, v ref = 4.096v f in = 20khz figure 16 . thd, sfdr vs. temperature
AD7699 rev. 0 | page 10 of 28 94 92 90 88 86 17 16 15 14 13 4.0 4.5 5.0 5.5 reference voltage (v) snr, sinad (db) enob (bits) 07354-016 f in = 20khz snr sinad enob figure 17. snr, sinad, en ob vs. reference voltage 95 94 93 92 91 90 89 88 87 86 85 15.6 15.5 15.4 15.3 15.2 15.1 15.0 14.9 14.8 14.7 14.6 ?10?8?6?4?2 0 input level (db) snr (db) enob (bits) 07354-018 f in = 20khz v ref = 5v snr sinad enob figure 18. snr, sinad, and enob vs. input level 3 2 1 0 ?1 ?2 ?3 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) zero error, gain error (lsb) 07354-020 unipolar offset unipolar gain bipolar gain bipolar offset figure 19. offset and gain errors vs. temperature, not normalized ? 80 ?85 ?90 ?95 ?100 ?105 ?110 110 105 100 95 85 90 80 4.0 4.5 5.0 5.5 reference voltage (v) thd (db) sfdr (db) 07354-019 sfdr thd figure 20. thd, sfdr vs. reference voltage 5500 5250 5000 4750 4500 180 140 100 60 160 120 80 40 20 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) v dd current (a) vio current (a) 07354-022 vio f s = 500ksps v dd , int ref v dd , ext ref figure 21. operating currents vs. temperature 5750 5500 5250 5000 4750 4500 4250 4000 3750 100 90 80 70 60 50 40 30 20 4.5 5.0 5.5 vdd supply (v) vdd current (a) vio current (a) f s = 500ksps 0 7354-040 vio external ref, temp on 4.096v internal ref external ref, temp off internal buffer, temp off internal buffer, temp on figure 22. operating currents vs. supply
AD7699 rev. 0 | page 11 of 28 4.099 4.098 4.097 4.096 4.095 4.094 4.093 4.092 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) v ref (v) 07354-041 figure 23 . internal reference output voltage vs. temperatur e, three d evices 07354-021 sdo ca p acitive load (pf) 120 0 20 40 60 80 100 t dsdo del ay (ns) 25 20 15 10 5 0 vdd = 5 v , 85c vdd = 5 v , 25c figure 24 . t dsdo delay vs. sdo capacitance load and supply
AD7699 rev. 0 | page 12 of 28 terminology least significant bit (lsb) the lsb is the smallest increment that can be represe nted by a converter. for a n analog - to - digital converter with n bits of resolution, the lsb expressed in volts is n ref v lsb 2 (v) = integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative f ull scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 26). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of reso lution for which no missing codes are guaranteed. offset error for unipolar mode, t he first transition should occur at a level ? lsb above analog ground. the unipolar offset error is the deviation of the actual transition from that point. for bipolar mode , the first transition should occur at a level ? lsb above v ref /2. the bipolar offset error is the deviation of the actual transition from that point. gain error the last transition (from 111 10 to 111 11) should occur for an analog voltag e 1? lsb belo w the nominal full scale. the gain error is the deviation in lsb (or percentage of full - scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. closely related is the full - scale error (also in ls b or percentage of full - scale range), which includes the effects of the offset error. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and the point at which the input sig nal is held for a conversion. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input s ignal and is expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the formula enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. channel -to - channel crosstalk channel - to - channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. it is m easured by applying a dc to the channel under test and applying a full- scale, 100 khz sine wave signal to the adjacent channel(s). the crosstalk is the amount of signal that leaks into the test channel and is expressed in decibels . reference voltage temperature coefficient reference voltage temperature coefficient is derived from the typical shift of output voltage at 25c on a sample of parts at the maximum and minimum reference output voltage (v ref ) meas - ured at t min , t (25c), and t max . it is expressed in ppm/c as 6 10 )C()c25( )(C)( )c ppm/ ( = min max ref ref ref ref tt v min v max v tcv where: v ref ( max ) = maximum v ref at t min , t (25c), or t max . v ref ( min ) = minimum v ref at t min , t (25c), or t max . v ref (25 c ) = v ref at 25c. t max = +85c. t min = C 40c.
AD7699 rev. 0 | page 13 of 28 theory of operation sw+ msb 16, 384c in x+ lsb comp contr ol l ogi c swit ch es contr ol bu sy output code cn v ref gnd in x? or com 4c 2c c c 32, 768c sw? msb 16, 384c lsb 4c 2c c c 32, 768c 07354-023 figure 25 . adc simplified schematic overview the AD7699 is an 8- channel , 16 - bit, charge redistribution successi ve approximation register (sar) analog - to - digital converter (adc). it is capable of converting 500 ,000 samples per second ( 500 ksps) and power down between conversions. for example, w hen operating with an external reference at 1 ksps, it consumes 52 w typically, ideal for battery - powered applications. the AD7699 contain s all of th e components for use in a multi channel, low power da ta acquisit ion system , including ? 16- bit sar adc with no missing codes ? 8- channel, low crosstalk multiplexer ? internal low drift reference and buffer ? temperature sensor ? selectable one - pole filter ? channel sequencer these components are configured through a n spi - compatibl e, 14- bit register. conversion results, also spi compatible, can be read after or during conversions with the option for reading back the configuration. the AD7699 provide s the user with an on - chip track - and - hold and do es not exhibit pipeline delay or late ncy. the AD7699 is specified from 4.5 v to 5.5 v and can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 20-lead, 4 mm 4 mm lfcsp that combines space savings and allows flexible configurations and is also pin - for - pin compatible with the 16- bit ad7682 and ad7689 , and the 14- bit ad7949 . converter operation the AD7699 is a successive approximatio n adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary - weighted capacitors, which are connected to the two comparator in puts. during the acquisition phase, terminals of the array tied to the comparator input are connected to gnd via sw+ and sw ?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acqu ire the analog signal on the in x + and in x ? ( or com) inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw ? are opened first. the two capacitor arrays are th en disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in x+ and in x? ( or com) inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref , the comparator input varies by binary - weighted voltage steps (v ref /2, v ref /4 , ... v ref /32,768). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the AD7699 has an on - board conversion cloc k, the serial clock, sck, is not required for the conversion process .
AD7699 rev. 0 | page 14 of 28 transfer functions with the inputs configured for unipolar range (single ended, com with ground sense, or paired differentially with inx? as ground sense), the data output is straight binary. with the inputs configured for bipolar range (com = v ref /2 or paired differentially with inx? = v ref /2), the data outputs are twos complement. the ideal transfer characteristic for the AD7699 is shown in figure 26 and for both unipolar and bipolar ranges with the internal 4.096 v reference. 100...000 100...001 100...010 011...101 011...110 011...111 twos complement straight binary 000...000 000...001 000...010 111...101 111...110 111...111 adc code analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 07354-024 figure 26. adc ideal transfer function table 6. output codes and ideal input voltages description unipolar analog input 1 v ref = 4.096 v digital output code (straight binary hex) bipolar analog input 2 v ref = 4.096 v digital output code (twos complement hex) fsr ? 1 lsb 4.095938 v 0xffff 3 2.047938 v 0x7fff 3 midscale + 1 lsb 2.048063 v 0x8001 62.5 v 0x0001 midscale 2.048 v 0x8000 0 v 0x0000 midscale ? 1 lsb 2.047938 v 0x7fff ?62.5 v 0xffff 4 ?fsr + 1 lsb 62.5 v 0x0001 ?2.047938 v 0x8001 ?fsr 0 v 0x0000 3 ?2.048 v 0x8000 1 with com or inx? = 0 v or all inx referenced to gnd. 2 with com or inx? = v ref /2. 3 this is also the code for an overranged analog input ((inx+) ? (inx?), or com, above v ref ? v gnd ). 4 this is also the code for an underranged analog input ((inx+) ? (inx?), or com, below v gnd ).
AD7699 rev. 0 | page 15 of 28 typical connection d iagram s AD7699 ref gnd vdd vio din mosi miso ss sck sck sdo cnv 100nf 100nf 5v 10f 2 v+ v? 1.8v to vdd 0v to v ref 0v to v ref v+ v? ada4841-x 3 ada4841-x 3 1. internal reference shown. see the voltage reference output/input section for reference selection. notes 2. c ref is usually a 10f ceramic capacitor (x5r). 3. see the driver amplifier choice section for additional recommended amplifiers. 4. see the digital interface section for configuring and reading conversion data. in0 in[7:1] com refin 100nf 0v or v ref /2 07354-025 figure 27 . typical application diagram with multiple supplies ref gnd vdd vio din mosi miso ss sck sck s do cnv 100nf 100nf 5v 10f 2 v+ 1.8v to vdd v+ notes 1. internal reference shown. see the voltage reference output/input section for reference selection. 2. c ref is usually a 10f ceramic capacitor (x5r). 3. see the driver amplifier choice section for additional recommended amplifiers. 4. see the digital interface section for configuring and reading conversion data. in0 in[7:1] com refin 100nf v ref /2 v ref p-p ada4841-x 3 ada4841-x 3 07354-026 AD7699 figure 28 . typical application diagram using bipolar input
AD7699 rev. 0 | page 16 of 28 unipolar or bipolar figure 27 shows an example of the recommended connection diagram for the AD7699 when multiple supplies are available. bipolar single supply figure 28 shows an example of a system with a bipo lar input using single supplies with the internal reference (optional different vio supply). this circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. note that for any input config - ur atio n, the inputs , in x, are unipolar and always referenced to gnd (no negative voltages even in bipolar range) . for this circuit, a rail - to - rail input/output amplifier can be used ; however, the offset voltage vs. input common - mode range should be noted and ta ken into consideration (1 lsb = 62.5 v with v ref = 4.096 v ). note that the conversion results are in two s complement format when using the bipolar input configuration. refer to the an - 581 application note , biasing and decoupling op amps in single supply applications , at www.analog.com for additional details about using single - supply amplifiers. analog inputs input structure figure 29 shows an equivalent circuit of the input structure of the AD7699 . the two diodes, d1 and d2, provide esd protection for the analog inputs, in[7:0] and com. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this caus es the diodes to become forward - biased and to start conducting cu rrent. these diodes can handle a forward - biased current of 130 ma maximum. for instance, these conditions may eventual ly occur when the input buffer supplies are different from vdd. in such a case, for example, an input buffer with a short circuit, the cu rrent limitation can be used to protect the part. c in r in d1 d2 c pin inx+ or inx? or com gnd vdd 07354-027 figure 29 . equivalent analog input circuit th is analog input structure allows the sampling of the true differential signal between in x + and com or in x + and in x?. (com or in x? = gnd 0.1 v or v ref 0.1 v). by using these differential inputs, signals common to both inputs are rejected , as shown in figure 30 . 70 65 60 55 50 45 40 35 30 1 10k 10 cmrr (db) 100 1k frequency (khz) 07354-028 figure 30 . analog i nput cmrr vs. frequency during t he acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? (8.8 k ? when the one - pole filter is active) and is a lumped component made up of serial resistors and the on resistance of the switches. c in is typically 27 pf and is mainly the adc sampling capacitor. selectable low - pass filter during the conversion phase, where the switches are opened, the input impedance is limited to c pin . while the ad76 99 is acquiring, r in and c in make a one - pole, low - pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. the low - pass filter can be programmed for the full bandw idth or ? of the bandwidth with cfg[6] , as shown in table 8 . note that the converter through p ut must also be reduced by ? when using the filter. if the max imum throughput is used with th e bw set t o ? , the acquisition time of the converter , t acq , is violated, result ing in poor thd. input configurations figure 31 shows the different methods for configuring the analog inputs with the configuration register ( cfg[ 1 2:10 ]). refe r to the configuration register, cfg section for more details.
AD7699 rev. 0 | page 17 of 28 gnd com ch 0+ ch 3+ ch 1+ ch 2+ ch 4+ ch 5+ ch 6+ ch 7+ ch 0+ ch 3+ ch 1+ ch 2+ ch 4+ ch 5+ ch 6+ ch 7+ com? gnd com in1 in0 in2 in3 in4 in5 in6 in7 in1 in0 in2 in3 in4 in5 in6 in7 in1 in0 in2 in3 in4 in5 in6 in7 in1 in0 in2 in3 in4 in5 in6 in7 a?8 chann els, single e nd ed b?8 chann els, common refere nc e gnd com ch 0+ (?) ch 1+ (?) ch 2+ (?) ch 3+ (?) ch 0? (+) ch 1? (+) ch 0+ (?) ch 1+ (?) ch 0? (+) ch 1? (+) ch 2? (+) ch 3? (+) c?4 chann els, di ff erenti al gnd com ch 2+ ch 3+ ch 4+ ch 5+ d?combi na t io n com? 07354-029 figure 31 . multiplexed analog input configurat ions the analog inputs can be configured as ? figure 31 a, s ingle - ended referenced to system ground ; cfg[ 12:10 ] = 111 2 . ? figure 31 b, bipolar differential with a common reference point; com = v ref /2; cfg[12:10] = 010 2 . unipolar d ifferential with com connected to a ground sense ; cfg[12:10] = 110 2 . ? figure 31 c, bipolar differential pairs with in x? referenced to v ref /2; cfg[12:10] = 00x 2 . unipolar d ifferential pairs with in x? referenced to a ground sense ; cfg[ 12:10 ] = 1 0x 2 . in this configuration, the in x + is identified by the cha nnel in cfg[9:7] . for e xample , for in 0 = in 1+ and in 1 = in 1?, cfg[9:7] = 000 2 ; for in 1 = in 1 + and in 0 = in 1?, cfg[9:7] = 001 2 . ? figure 31 d, inputs configured in any of the above combinations (showing that the AD7699 can be configur ed dynamically ). sequencer the AD7699 include s a channel sequencer useful for scanning channels in a in 0 to in [7: 0 ] fashion. channels are scanned as sin gles or pairs , with or without the temperature sensor , after the last channel is sequenced . the sequenc er starts with in 0 and finishes with in [7: 0 ] set in cfg[ 9:7] . for paired channels, the channels are paired depending on the last channel set in cfg[9:7] . note that the channel pairs are always paired as in ( even ) = inx+ and in ( odd ) = inx ? regardless of cfg[7] . to enable the sequencer, cfg[2:1] are written to for initializing the sequencer. after cfg [13:0] are updated, din must be held low while reading data out (at least for b it 13) , or the cfg register begin s updating again. while opera ting in a sequence, the cfg register can be changed by writing 01 2 to cfg[2:1] . however, if changing cfg 11 (paired or single channel) or cfg[9:7] (last channe l in sequence), the sequence reinitialize s and convert s in 0 (or in 1) after cfg is updated. exampl es bit[13], bits[6:3], and bit 0 are configured for the inpu t and sequencer. as a first example, scan all in [7:0] referenced to com = gnd with the temperature sensor . 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg in cc inx bw ref seq rb 1 1 0 1 1 1 1 0 as a second ex ample, s can three paired channels without the temperature sensor and referenced to v ref /2 . 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg incc inx bw ref seq rb 0 0 x 1 1 0 x 1 1 1 1 x = dont care. source resistance when the source impedance o f the driving circuit is low, the AD7699 can be driven directly. large source impedances signifi- cantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency .
AD7699 rev. 0 | page 18 of 28 driver amplifier cho ice although the AD7699 is easy to driv e, the driver amplifier must meet the followi ng requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the AD7699 . note that the ad76 99 ha s a noise much lower than most of the other 16 - bit adcs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. the noise from the amplifier is filtered by the AD7699 analog input circuit low - pass filter made by r in and c in or by an external filter, if one is used. because the typical noise of the AD7699 is 35 v rms (with v ref = 5 v) , the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 )( 2 35 35 log20 n 3db loss ne f snr where: f ? 3db is the input bandwidth in megahertz of the AD7699 ( 14.7 mhz in full bw or 670 khz in ? bw) or t he cutoff frequency of an input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp , in nv/ hz. ? for ac applications, the driver should have a thd perfor - mance commensurate with the AD7699 . figure 12 shows thd vs. frequency for the AD7699 . ? for multichannel, multiplexed application s on each input or input pair, the driver amplifier and the ad76 99 analog input circuit must settle a full - scale step onto the capacitor array at a 16 - bit le vel (0.0015%). in amplifier data sheet s, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at a 16 - bit level and should be verified prior to driver selection. table 7 . recommended driver amplifiers amplifier typical application a da4841 -x very low noise, small, and low power ad8655 5 v single supply, low noise ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single supply, low power voltage reference output / in put the AD7699 allows the choice of a very low temperature dr ift internal voltage reference, an external reference , or an exter nal buffered reference. the internal reference of the AD7699 provide s excel l ent performance an d can be used in almost all applications. there are five possible choices of voltage reference schemes briefly described in table 8 with more details in each of the following sections. internal reference/temperature sensor the in ternal reference can be set for a 4.096 v output as detailed in table 8 . with the inter nal reference enabled, the band gap voltage is also present on the ref in pin, which requires an external 0.1 f capacitor. because the current output of refin is limited, it can be used as a source if followed by a suitable buffer , such as the ad8605 . enabling the reference also enables the internal temperature sensor, which measures the internal temper ature of the AD7699 and is thus useful for performing a system calibration. note that , when using the temperature sensor , the output is straight binary refe r enced from the AD7699 gnd pin. the internal reference is temperature - compensated to within 15 m v. the reference is trimmed to provide a typical drift of 3 ppm/c. external reference and internal buffer for improved drift performance , an external reference can be used with the internal buffer . the external reference is connected to ref in , and the outpu t is produced on the ref pin. a n external reference can be used with the internal buffer with or without the temperature sensor enabled . refer to table 8 for register details. wit h the buffer enabled, the gain i s unity and is limi ted to an input/output of 4.096 v. the internal reference buffer is useful in multiconverter appli ca - tions because a buffer is typically required in these applications . in addition , a low power reference can be used because the internal buffer provides the necessary performance to drive the sar architecture of the AD7699 . external reference in any of the five voltage reference schemes , an external refer - ence can be connected directly on the ref pin because the output impedance of ref is > 5 k . to reduce power consumption, the reference and buffer can be powered down independently or together for the lowest power consumption. however, for applica - tions requi r ing the use of the temperature sensor, the reference must be active . refer to table 8 for register details. for improved drift performance, an external reference such as the adr43x or adr44 x is recommended. reference deco upling whether using an internal or external reference, the ad76 99 voltage reference output/ input , ref , has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins. this deco upling depends on the choice of the voltage reference but usually consists of a low esr capacitor connected to ref and gnd with minimum parasitic inductance . a 10 f (x5r, 1206 size) ceramic chip capacitor is appropriate when using the internal reference , the adr43x / adr44x external
AD7699 rev. 0 | page 19 of 28 reference , or a low impedance buffer such as the ad8031 or the ad8605 . the placement of the reference decoupling capacitor is also important to the performance of the AD7699 , as explained in the layout section. mount t he decoupling capacitor on the same side as the adc at t he ref pin with a thick pcb trace. the gnd should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. if desired, smaller reference decoupling capacitor values down to 2.2 f can b e used with a minimal impact on performance, especially on dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. for applications that use multiple AD7699 s or other pulsar devices, it is more effective to use the internal reference buffer to buffer the external reference voltage , thus reducing sar conversion crosstalk . the voltage reference temperature coefficient (tc) directly impacts full scale; therefore, in applications where full - scale accuracy matters, care must be taken with the tc. for instance, a 15 ppm/c t c of the reference changes full scale by 1 lsb/c . power supply the AD7699 uses two power supply pins : an analog and digital core supply ( vdd ) and a digi tal input/output interface supply ( vio ) . vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd pins can be tied together. the AD7699 is independent of power supply sequencing between vio and vdd. t he only restriction is that cnv must be low when powering up the AD7699 . additionally, it is very insensitive to power supply variations over a wide frequency range , as shown in figure 32 . 75 70 65 60 55 50 45 40 35 30 1 10k 10 pssr (db) 100 1k frequency (khz) 07354-030 figure 32 . psr r vs. frequency the AD7699 power s down automatically at the end of each conversion phase ; therefore, the operating currents and power scale linearly with the sampling rate . this makes the part ideal for low sampling rate s (even of a few hertz) and low bat tery - powered applications. 10,000 1000 100 10 1 0.1 0.010 0.001 10 1m 100 operating current (a) 1k 10k 100k sampling rate (sps) 07354-031 vdd = 5v, internal ref vdd = 5v, external ref vio figure 33 . operating c urrents vs. sampl ing rate supplying the adc fr om the reference for simplified applications, the AD7699 , with its low operating current, can be supplied directly using the referen ce circuit , as shown in figure 34 . the reference line can be driven by ? t he system power supply directly ? a reference voltage with enough current output capability, such as the adr43x / adr44x ? a reference buffer, such as the ad8605 , which can also filter the system power supply, as shown in figure 34 ad 860 5 AD7699 vio ref vdd 10f 1f 0.1f 10 ? 10k? 5v 5v 5v 1f 1 1 optiona l reference buffer and fi l ter. 0.1f 07354-032 figure 34 . example of an application circuit
AD7699 rev. 0 | page 20 of 28 digital interface the AD7699 uses a simple 4-wire interface and is compatible with spi, microwire?, qspi?, digital hosts, and dsps, for example, blackfin? adsp-bf53x, sharc?, adsp-219x, and adsp-218x. the interface uses the cnv, din, sck, and sdo signals and allows cnv, which initiates the conversion, to be independent of the readback timing. this is useful in low jitter sampling or simultaneous sampling applications. a 14-bit register, cfg[13:0], is used to configure the adc for the channel to be converted, the reference selection, and other components, which are detailed in the configuration register, cfg section. when cnv is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conver- sion), as detailed in the following sections. the cfg word is updated on the first 14 sck rising edges, and conversion results are output on the first 15 (or 16 if busy mode is selected) sck falling edges. if the cfg readback is enabled, an additional 14 sck falling edges are required to output the cfg word associated with the conversion results, with the cfg msb following the lsb of the conversion result. a discontinuous sck is recommended because the part is selected with cnv low, and sck activity begins to write a new configuration word and clock out data. note that in the following sections, the timing diagrams indicate digital activity (sck, cnv, din, sdo) during the conversion. however, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading/ writing time, t data , because the AD7699 provides error correction circuitry that can correct for an incorrect bit during this time. from t data to t conv , there is no error correction and conversion results may be corrupted. the user should configure the AD7699 and initiate the busy indicator (if desired) prior to t data . it is also possible to corrupt the sample by having sck or din transitions near the sampling instant. therefore, it is recommended to keep the digital pins quiet for approximately 30 ns before and 10 ns after the rising edge of cnv, using a discontinuous sck whenever possible to avoid any potential performance degradation. reading/writing during conversion, fast hosts when reading/writing during conversion (n), conversion results are for the previous (n ? 1) conversion, and writing the cfg is for the next (n + 1) acquisition and conversion. after the cnv is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion. reading/writing should only occur up to t data and, because this time is limited, the host must use a fast sck. the sck frequency required is calculated by data t edgessck number sck f __ ? the time between t data and t conv is a safe time when digital activity should not occur, or sensitive bit decisions may be corrupt. reading/writing during acquisition, any speed hosts when reading/writing after conversion, or during acquisition (n), conversion results are for the previous (n ? 1) conversion, and writing is for the (n + 1) acquisition. for the maximum throughput, the only time restriction is that the reading/writing take place during the t acq (min) time. for slow throughputs, the time restriction is dictated by throughput required by the user, and the host is free to run at any speed. thus for slow hosts, data access must take place during the acquisition phase. reading/writing spanning conversion, any speed host when reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n). conversion results are for the previous (n ? 1) conversion, and writing the cfg register is for the next (n + 1) acquisition and conversion. similar to reading/writing during conversion, reading/writing should only occur up to t data . for the maximum throughput, the only time restriction is that reading/writing take place during the t acq (min) + t data time. for slow throughputs, the time restriction is dictated by the users required throughput, and the host is free to run at any speed. similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion. note that data access spanning conversion requires the cnv to be driven high to initiate a new conversion, and data access is not allowed when cnv is high. thus, the host must perform two bursts of data access when using this method. configuration register, cfg the AD7699 uses a 14-bit configuration register (cfg[13:0]) as detailed in table 8 for configuring the inputs, the channel to be converted, one-pole filter bandwidth, the reference, and the channel sequencer. the cfg register is latched (msb first) on din with 14 sck rising edges. cfg update is edge dependent, allowing for asynchronous or synchronous hosts.
AD7699 rev. 0 | page 21 of 28 the register c an be written to during conversion, during acquisi - tion, or spanning acquisition/ conversion and is updated at the end of conversion, t conv (max imum ). there is always a one deep delay when writing the cfg register . note that at power - up, the cfg register is undefined and two dummy conversions are required to update the register. to preload the cfg register with a factory setting, hold din high for two conversions. thus cfg[13:0] = 0 x3fff. this sets the AD7699 for the following: ? in[7:0] unipolar referenced t o gnd, sequenced in order ? full bandwidth for a one - pole filter ? internal reference/temp erature sensor disabled, buffer enabled ? enables the sequencer ? no read back of the cfg register table 8 summarizes the configuration regist er bit details. see the theory of operation section for more details . 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg incc incc incc in x in x in x bw ref ref ref seq seq rb table 8 . configuration register description bit (s ) name description [ 13 ] cfg configuration u pdate . 0 = keep current configuration settings. 1 = overwrite contents of register. [ 12:10 ] incc input c hannel c onfiguration . selection of pseudobipolar, pseudo differential, pairs , single - ended , or temper ature sensor. refer to the input configurations section. bit 12 bit 11 bit 10 function 0 0 x 1 bipolar differential pairs; inx ? referenced to v ref /2 0.1 v. 0 1 0 bipolar; inx referenced to com = v ref /2 0.1 v. 0 1 1 temperature sensor. 1 0 x 1 unipolar differential pairs; inx ? referenced to gnd 0.1 v. 1 1 0 unipolar, in0 to in7 referenced to com = gnd 0.1 v (gnd sense). 1 1 1 unipolar, in0 to in7 referen ced to gnd. [ 9:7 ] inx input c hannel s election in b inary f ashion . bit 9 bit 8 bit 7 channel 0 0 0 in0 0 0 1 in1 1 1 1 in7 [6] bw select b andwidth for low-p ass f ilter . refer to the selectable low - pass filter section. 0 = ? of bw, uses an additional series resistor to further bandwidth limit the noise. maximum throughput must also be reduced to ?. 1 = full bw. [ 5:3 ] ref reference/b uffer s election . sel ection of internal, external, and external buffered references , and enabling of the on - chip temperature sensor. refer to the voltage reference output/input section. bit 5 bit 4 bit 3 function 0 0 0 not used 0 0 1 intern al reference, ref = 4.096 v output. 0 1 0 external reference, temperature enabled. 0 1 1 external reference, internal buffer, temperature enabled. 1 1 0 external reference, temperature disabled. 1 1 1 external reference, internal buffer, temper ature disabled. [ 2:1 ] seq channel s equencer . allows for scanning channels in an in0 to in [7: 0] f ashion. refer to the sequencer section. bit 2 bit 1 function 0 0 disable sequencer. 0 1 update configuration during seque nce. 1 0 scan in0 to in [7: 0] (se t in cfg[9:7]), then temperature. 1 1 scan in0 to in [7: 0] (se t in cfg[9:7]). 0 rb read back the cfg r egister . 0 = read back current configuration at end of data. 1 = do not read back contents of configuration. 1 x = dont care.
AD7699 rev. 0 | page 22 of 28 general timing without a busy indicator figure 35 details the timing for all three modes: reading/writing during conversion, after conversion, and spanning conversion. note that the gating item for both cfg and data readback is at the end of conversion (eoc). at the end of conversions (eoc), if cnv is high, the busy indicator is disabled. as detailed previously, the data access should occur up to safe data reading/writing time, t data . if the full cfg word was not written to prior to eoc, it is discarded and the current configuration remains. if the conversion result is not read out fully prior to eoc, it is lost as the adc updates sdo with the msb of the current conversion. for detailed timing, refer to figure 36 and figure 37, which depict reading/writing spanning conversion with all timing details, including setup, hold, and sck. when cnv is brought low after eoc, sdo is driven from high impedance to the msb. falling sck edges clock out bits starting with msb ? 1. the sck can idle high or low depending on the clock polarity (cpol) and clock phase (cpha) settings if spi is used. a simple solution is to use cpol = cpha = 0 as shown in figure 35 with sck idling low. 07354-033 phase cnv cnv cnv din sdo read/write during convert read/write after convert read/write spanning convert din sdo din sdo sck sck sck notes 1. cnv must be high prior to the end of conversion (eoc) to avoid the busy indicator. a total of 16 sck falling edges is required to return sdo to high-z. if cfg readback is enabled, a total of 30 sck falling edges is required to return sdo to high-z. t cyc t conv t data 1 acquisition (n ? 1) acquisition (n) acquisition (n + 1) acquisition (n + 2) conversion (n ? 1) conversion (n) conversion (n + 1) conversion (n ? 2) data (n ? 2) data (n ? 2) data (n ? 1) data (n ? 1) data (n) data (n) data (n + 1) cfg (n) cfg (n + 2) cfg (n + 1) cfg (n + 3) 1 16/30 1 16/30 1 16/30 1 16/30 1 16/30 1 16/30 1 16/30 1 1 16/30 1 16/30 1 16/30 data (n ? 2) data (n ? 1) data (n + 1) data (n) cfg (n) cfg (n + 1) cfg (n + 2) cfg (n + 3) xxx data (n ? 2) data (n ? 1) data (n) xxx cfg (n) cfg (n + 1) cfg (n + 2) msb (n ? 1) msb (n + 1) msb (n) msb (n ? 2) end of conversion (eoc) start of conversion eoc eoc power up figure 35. general interface timing fo r the AD7699 without a busy indicator
AD7699 rev. 0 | page 23 of 28 read/write spann ing conversion without a b usy indicator this mode is used when the AD7699 is connected to an y host usin g an spi, serial port , or fpga. the connection diagram is shown in figure 36 , and the corresponding timing is given in figure 37. for spi , the host should use cpha = cpol = 0. r eading/writing spannin g conversion is shown , which covers all three modes detailed in the digital interface section. for this mode, the host must generate the data transfer based on the conversion time. for an interrupt driven transfer, refer to the ne xt section, which uses a busy indicator. a rising edge on cnv initiates a conversion, forces sdo to high impedance, and ignores data present on din. after a conversion is initiated, it continues until completion irrespective of the state of cnv. cnv must be returned high before the safe data transfer time, t data , and then held high beyond the conver - sion time, t conv , to avoid generation of the busy signal indicator. after the conversion is complete, the AD7699 enters the acquisi - tion phase and powers down . when the host brings cnv low after t conv (max), the msb is enabled on sdo. the host also must enable the msb of cfg at this time (if necessary) to begin the cfg update. while cnv is low, both a cfg update and a data readback take place. the first 14 sck rising edges are used to update the cfg, and the first 15 sck falling edges clock out the conversion results starting with msb ? 1. the restriction for both configuring and reading is that they both must occur before the t data time of the next conversion elapses. all 14 bits of cfg[13:0] must be written, or they are ignored. in addition, if the 16 - bit conversion result is not read back before t data elapses, it is lost. the sdo data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th (or 30 th ) sck falling edge, or when cnv goes high (whichever occurs first), sdo returns to high impedance. if cfg re adback is enabled, the cfg associated with the conver - sion result is read back msb first following the lsb of the conversion result. a total of 30 sck falling edges is required to return sdo to high impedance if this is enabled. miso mosi sck ss cnv for spi use cph a = 0, cpo l = 0. sck s do din AD7699 digital host 07354-034 figure 36 . connection diagram for the AD7699 w ithout a busy indicator update (n) cfg/sdo up dat e (n + 1) cfg/sdo acquisition (n) acquisition (n + 1) acquisition (n ? 1) msb msb ? 1 1 2 begin data (n ? 1) begin cfg (n + 1) cfg msb cfg msb ? 1 lsb + 1 14 15 see note see note notes 1. the lsb is for conversion results or the configuration register cfg (n ? 1) if. 15 sck falling edges = lsb of conversion results. 29 sck falling edges = lsb of configuration register. on the 16th or 30th sck falling edge, sdo is driven to high impendance. 16/ 30 conversion (n) return cnv high for no busy end data (n ? 1) end cfg (n + 1) cfg lsb x x > t conv lsb sck cnv din sdo lsb + 1 14 15 16/ 30 conversion (n ? 1) return cnv high for no busy end data (n ? 2) end cfg (n) cfg lsb x x t conv t data t cnvh t data t dis t dis t en t dsdo t hsdo t hdin t sdin t clsck t en t en t sck t sckh t sckl t dis t dis t conv lsb 07354-035 t acq t cyc (quiet time) (quiet time) figure 37 . serial interface timin g for the AD7699 without a busy indicator
AD7699 rev. 0 | page 24 of 28 general timing with a busy indicator figure 38 details the timing for all three modes : reading/writing during conversion, after conversion, and spanning conversion. note that the gating item for both cfg and data readback is at the end o f conversion (eoc). as detailed previously, the data access should occur up to safe data reading/writing time, t data . if the full cfg word is not written to prior to eoc, it is discarded and the current configuration remain s. at the eoc, if cnv is low, the busy indicator is enabled. in addition, to generate the busy indicator p roperly, the host must assert a minimum of 17 sck falling edges to return sdo to high impedance because the last bit of data on sdo remain s active. unlike the case detailed in the general timing without a busy indicator section, if the conversion result is not read out fully prior to eoc, the last bit clocked out remain s . if this bit is low, the busy signal indicator cannot be generated because the digital output requires a high impedance, or a bit remaining high, to low transition for the interrupt input of the host . a good example of this occurs when an spi host sends 16 scks because these are usually limited to 8 - bit or 16 - bit bursts, thus the lsb remains. because the transition noise of the ad76 99 is 4 lsbs peak to peak (or grea ter), the lsb is low 50% of the time. for this interface , the spi host needs to burst 24 scks , or a qspi interface can be used and programmed for 17 scks. the sck can idle high or low depending on the cpol and cpha settings if spi is used. a simple solutio n is to use cpol = cpha = 1 (not shown) with sck idling high. t cyc t conv t data power up end of conversion (eoc) start of conversion eoc eoc acquisition (n ?1) acquisition (n) acquisition (n + 1) acquisition (n + 2) conversion (n ? 1) conversion (n) conversion (n + 1) conversion (n ? 2) read/write during convert read/write after convert read/write spanning convert phase cnv cnv cnv din sdo din sdo din sdo sck sck sck 07354-036 notes 1. cnv must be high prior to the end of conversion (eoc) to avoid the busy indicator. a total of 17 sck falling edges is required to return sdo to high-z. if cfg readback is enabled, a total of 31 sck falling edges is required to return sdo to high-z. data (n ? 2) data (n ? 2) data (n ? 1) data (n ? 1) data (n) data (n) data (n + 1) cfg (n) cfg (n + 2) cfg (n + 1) cfg (n + 3) xxx data (n ? 2) data (n ? 1) data (n) 1 17/31 1 17/31 1 17/31 1 1 17/31 1 17/31 1 17/31 1 1 17/31 1 17/31 1 17/31 1 17/31 xxx cfg (n) cfg (n + 1) cfg (n + 2) data (n ? 2) data (n ? 1) data (n) data (n + 1) cfg (n) cfg (n + 1) cfg (n + 2) cfg (n + 3) figure 38 . general interface timing for the ad76 99 with a busy indicator
AD7699 rev. 0 | page 25 of 28 read/write spanning conver sion w ith a busy indicator this mode is used when the AD7699 is connected to any host using an spi, serial port , or fpga with an interrupt input . the connection diagram is shown in figure 39 , and the corres pon ding timing is given in figure 40. for spi, the host shoul d use cpha = cpol = 1. reading/writing spanning conversion is shown , which covers all three modes detailed in the digital interface section. a rising edge on cnv initiates a conversion, forces sdo to high impedance, and ignores da ta present on din. after a conversion is initiated, it continues until completion irrespec - tive of the state of cnv. cnv must be returned low before the safe data transfer time, t data , and then held low b eyond the conversion time, t conv , to generat e the bu sy signal indicator. when the conversion is complete, sdo transitions from high impedance to l ow with a pull - up to vio, which can be used to interrupt the host to begin data transfer. after the conversion is complete, the AD7699 enter s the acquisition ph ase and power - down. the host must enable the msb of cfg at this time (if necessary) to begin the cfg update. while cnv is low , both a cfg update and a data read back take place. the first 14 sck rising edges are used to update the cfg register, and the firs t 1 6 sck falling edges clock out the conversion results starting with the msb. the restriction for both configuring and reading is that they both occur before the t data time elapses for the next conversion. all 14 bits of cfg[13:0] must be written or they are ignored. also , if the 16 - bit conversion result is not read back before t data elapses, it is lost. the sdo data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a fast er reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge , sdo returns to high impedance. note that , if the optional sck falling edge is not used, the busy feature cannot be detected if the lsb for the conversion is low. if cfg readback is enabled, the cfg register associated with the conversion result ( n ? 1 ) is read back msb first following the lsb of the conversion result. a total of 3 1 sck falling edges is required to return sdo to high impedance if this is enab led. AD7699 miso mosi sck ss sdo vio for spi use cpha = 1, cpol = 1. sck cnv din digital host irq 07354-037 figure 39 . connection diagram for the AD7699 with a busy indicator sck acquisition (n) acquisition (n + 1) cnv din sdo msb msb ? 1 1 2 begin data (n ? 1) beign cfg (n + 1) cfg msb lsb + 1 lsb 15 15 see note see note notes 1. the lsb is for conversion results or the configuration register cfg (n ? 1) if. 16 sck falling edges = lsb of conversion results. 30 sck falling edges = lsb of configuration register. on the 17th or 31st sck falling edge, sdo is driven to high impendance. otherwise, the lsb remains active until the busy indicator is driven low. 16 16 17/ 31 17/ 31 conversion (n) conversion (n ? 1) (quiet time) end data (n ? 2) end data (n ? 1) end cfg (n + 1) end cfg (n) x x x x x x t data update (n + 1) cfg/sdo lsb + 1 lsb conversion (n ? 1) (quiet time) update (n) cfg/sdo t cyc t acq t hdin t hsdo t dsdo t sdin t data t conv t cnvh t dis t dis t dis t en t en t en cfg msb ?1 07354-038 t sck t sckh t sckl figure 40 . serial interface timing for the AD7699 with a busy indicator
AD7699 rev. 0 | page 26 of 28 application hints layout the printed circuit board that houses the AD7699 should be designed so that the analog and digital sections are separate d and confined to certain areas of the board. the pinout of the AD7699 , with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7699 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. cross over of digital and analog signals should be avoided. at least one ground plane should be used. it c an be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the AD7699 . the AD7699 voltage ref erence input , ref , has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them wit h wide, low impedance traces. finally, the power supplies , vdd and vio , of the ad76 99 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the AD7699 and connected using short , wide traces to provide low impedance paths and to red uce the effect of glitches on the power supply lines. evaluating AD7699 performance other recommended layouts for the AD7699 are outlined in the documentation of the evaluation board for the AD7699 ( e va l - ad7 6muxcbz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the evaluation controller board , e va l - control brd3 .
AD7699 rev. 0 | page 27 of 28 outline dimensions 2.65 2.50 sq 2.35 3.75 bsc sq 4.00 bsc sq compliant to jedec standards mo-220-vggd-1 090408-b 1 0.50 bsc pin 1 indic at or 0.50 0.40 0.30 top view 12 max 0.80 max 0.65 ty p sea ting plane pin 1 indic at or coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 41 . 20- lead lead frame chip scale package (lfcsp_vq) 4 mm 4 mm body, very thin quad (cp - 20 - 4) dimensions shown in millimeters ordering guide model integral nonlinearity no missing code temperature range package description package option ordering quantity AD7699 bcp z 1 1.5 lsb max 16 bits ?40c to +85c 20- lead lfcsp_vq cp -20 -4 tray, 490 AD7699 bcp zrl7 1 1.5 ls b max 16 bits ?40c to +85c 20- lead lfcsp_vq cp -20 -4 reel, 1500 eval - ad76 99 cbz 1 evaluation board eval - control brd3 z 1 , 2 controller board 1 rohs compliant part. 2 this controller board allows a pc to control and communicate with all analog devices evaluation boards whose model numbers en d in cb.
AD7699 rev. 0 | page 28 of 28 notes ? 2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07354 -0- 10/08(0)

▲Up To Search▲

Price & Availability of AD7699

	To Download AD7699 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .